Fitting more transistors onto a single die is desirable to reduce cost of electronics and improve their functional capability. A common strategy employed by semiconductor manufacturers is to simply reduce gate size of a field effect transistor (FET), and proportionally shrink area of the transistor source, drain, and required interconnects between transistors. However, a simple proportional shrink is not always possible because of what are known as “short channel effects”. Short channel effects are particularly acute when channel length under a transistor gate is comparable in magnitude to depletion depth of an operating transistor, and include reduction in threshold voltage, severe surface scattering, drain induced barrier lowering (DIBL), source-drain punch through, and electron mobility issues.
Conventional solutions to mitigate some short channel effects can involve implantation of pocket or halo implants around the source and the drain. Halo implants can be symmetrical or asymmetrical with respect to a transistor source and drain, and typically provide a smoother dopant gradient between a transistor well and the source and drains. Unfortunately, while such implants improve some electrical characteristics such as threshold voltage rolloff and drain induced barrier lowering, the resultant increased channel doping adversely affects electron mobility, primarily because of the increased dopant scattering in the channel.
Many semiconductor manufacturers have attempted to reduce short channel effects by employing new transistor types, including fully or partially depleted silicon on insulator (SOI) transistors. SOI transistors are built on a thin layer of silicon that overlies an insulator layer, have an undoped or low doped channel that minimizes short channel effects, and do not require either deep well implants or halo implants for operation. Unfortunately, creating a suitable insulator layer is expensive and difficult to accomplish. Early SOI devices were built on insulative sapphire wafers instead of silicon wafers, and are typically only used in specialty applications (e.g. military avionics or satellite) because of the high costs. Modern SOI technology can use silicon wafers, but require require expensive and time consuming additional wafer processing steps to make an insulative silicon oxide layer that extends across the entire wafer below a surface layer of device-quality single-crystal silicon.
One common approach to making such a silicon oxide layer on a silicon wafer requires high dose ion implantation of oxygen and high temperature annealing to form a buried oxide (BOX) layer in a bulk silicon wafer. Alternatively, SOI wafers can be fabricated by bonding a silicon wafer to another silicon wafer (a “handle” wafer) that has an oxide layer on its surface. The pair of wafers are split apart, using a process that leaves a thin transistor quality layer of single crystal silicon on top of the BOX layer on the handle wafer. This is called the “layer transfer” technique, because it transfers a thin layer of silicon onto a thermally grown oxide layer of the handle wafer.
As would be expected, both BOX formation or layer transfer are costly manufacturing techniques with a relatively high failure rate. Accordingly, manufacture of SOI transistors not an economically attractive solution for many leading manufacturers. When cost of transistor redesign to cope with “floating body” effects, the need to develop new SOI specific transistor processes, and other circuit changes is added to SOI wafer costs, it is clear that other solutions are needed.
Another possible advanced transistor that has been investigated uses multiple gate transistors that, like SOI transistors, minimize short channel effects by having little or no doping in the channel. Commonly known as a finFET (due to a fin-like shaped channel partially surrounded by gates), use of finFET transistors has been proposed for transistors having 28 nanometer or lower transistor gate size. But again, like SOI transistors, while moving to a radically new transistor architecture solves some short channel effect issues, it creates others, requiring even more significant transistor layout redesign than SOI. Considering the likely need for complex non-planar transistor manufacturing techniques to make a finFET, and the unknown difficulty in creating a new process flow for finFET, manufacturers have been reluctant to invest in semiconductor fabrication facilities capable of making finFETs.